1. Field of the Invention
The present invention relates to a thin film transistor, and more particularly, to a thin film transistor and its fabrication process for reducing leakage current and the number of masks required.
2. Discussion of the Related Art
Many studies have been made of the application of a polysilicon thin film transistor to the active device and peripheral circuits of an active matrix liquid crystal display. A laser annealing is used in the production of thin film transistors using polysilicon. By using a laser annealing, low temperature processes are available for fabrication, and high field effect mobility can be realized.
When polysilicon thin film transistors are used in a liquid crystal display, there are no problems with switching the driving circuit at high frequency due to the characteristics of polysilicon. However, leakage current may increase due to high drain current in the OFF state in the pixel array. Studies are currently conducted on thin film transistors having lightly doped drain (LDD) structures, or offset structures, to decrease the drain electric field, thereby reducing the leakage current. Producing a thin film transistor with an LDD structure or offset gate structure requires additional masking processes compared to producing a conventional thin film transistor.
FIGS. 1A-1D are flow diagrams illustrating a process for fabricating thin film transistors having an offset structure according to conventional techniques.
Referring to FIG. 1A, an amorphous silicon layer is formed on an insulating layer 10 and crystallized by laser annealing. The crystallized silicon layer is patterned by photolithography (using a first mask) to form an active layer 11.
Referring to FIG. 1B, an insulating layer and a metal layer are sequentially formed on the entire surface of the substrate above the insulating layer 10, and patterned by photolithography (using a second mask) to form gate electrodes 13 and a gate insulating layer 12. Reference numeral 11C indicates the channel region of the active layer overlapping the gate electrode 13.
Referring to FIG. 1C, the entire surface is coated with a photosensitive material, and then a photoresist pattern PR is formed (using a third mask), which covers the gate electrode, but exposes a part of the active layer 11. The photoresist pattern defies an offset region 11f.
The entire surface is then doped with an impurity to form ohmic regions in the exposed portions of active layer 11. The ohmic regions are a source region 11S and a drain region 11D. Parts of the active layer are blocked from being doped with impurity by the photoresist pattern PR. Thus, the blocked parts of the active layer, except for the channel region 11C, are offset regions 11f.
Referring to FIG. 1D, insulating material is deposited on the entire surface to form an insulating interlayer 14. The insulating interlayer 14 is patterned by photolithography (using a fourth mask) to form contact holes T exposing the source and drain regions 11S and 11D of the active layer 11.
Referring to FIG. 1E, a metal layer is formed on the entire surface above the insulating layer 10. The metal layer is patterned by a photolithography (using a fifth mask) to form source and drain electrodes 15S and 15D, which are connected to the source and drain regions 11S and 11D which were exposed by the contact hole.
In the fabrication process described above, it is necessary to perform five photolithography processes using five masks. In the fabrication of thin film transistors, reducing the number of masking process is as important as reducing the leakage current at the OFF state. This is because the photolithography is a sequential process, which requires complicated and precise processing, such as masking process, photoresist coating, and exposure and development. Therefore reducing the number of masking process desirably affects the productivity and reliability of fabricated products.